The method and system and is particularly useful in, but not limited to the passive verification of analog and mixed signal integrated circuits.
Electronic design automation (EDA) is software for designing electronic blocks. There are several broad types of electronic signals, components and blocks, digital, analog and a mixture of digital and analog termed mixed signal. The electronic design generally comprises at least one of the following levels of circuit information, a system level, an architectural level, a dataflow level, an electrical level, a device level and a technology level and/or the like.
Digital signals have discrete input and output values “0” and “1”, occurring at discrete time values, typically tied to a clock signal. Digital components which input and output the digital signals typically have static pin outs and interaction protocols. Digital blocks comprised of the digital components have well established and well documented physical layouts and electrical interactions. The simulators for digital blocks are discrete time event driven simulators.
Analog signals generally have continuous input and output values that may vary over time. Analog components typically have customizable layouts, in order to modify inputs, outputs, triggers, biases, etc. Therefore, due to customization, analog blocks comprised of the analog components, may not have well established or well documented physical layouts or electrical interactions. The simulators for analog blocks generally necessitate continuous time domain simulators.
Mixed signal blocks are a combination of digital signal blocks and analog signal blocks within a component being simulated. The most common options available for simulation are to simulate the component as a grouping of analog blocks, or, to separately analyze the analog components/blocks and the digital components/blocks and translate the inputs and outputs at the boundaries of the digital and analog domains for inter-domain communication.
Within EDA there are two broad categories of circuit review that are often related, simulation and verification. Simulation is a numerical solution set that predicts the behavior of a circuit. Verification is the systematic pursuit of describing the behavior of a circuit under relevant conditions (functional verification) and over manufacturing process variation (parametric verification). Therefore, verification generally necessitates a much more extensive review of the circuit, its operating conditions and manufacturing operation variations than a simulation. It is possible to run a large number of simulations without verifying to any significant degree the functionality of a circuit. Verification is the mathematical modeling of circuit behavior and evaluation of circuit performance over a range of conditions. Ultimately, the measure of success of verification is to report how well the circuit design complies with the circuit specification. Analog and mixed signal verification methodology is struggling to keep pace with the complexity, cost, and computational demands of ever-growing analog and mixed signal circuits.
The number and complexity of verification test cases grows with the complexity of analog and mixed signal designs. Additionally, simulation speed decreases and memory utilization increases as the size of the circuit grows. Thus, the computational processing-power to verify a circuit may dramatically increase with circuit complexity. To make this issue more painful, verification occurs at the end of a design cycle where schedule delays are perceived to be most severe. Thus, verification is an activity that generally necessitates a significant amount of simulation processing-power for a small part of the overall design cycle, and the efficient use of verification resources is generally necessitated to meet time to market demands.
Today's complex verification solutions specifically focus engineering on the verification activity to ensure that the operation of the circuit is fully and efficiently verified under at least most pertinent conditions. This focused analog and mixed signal verification is much more manual and experience driven than digital verification. There is a long felt need to gain as much information from the verifications that have been run to reduce duplicate simulations and to insure that primary and secondary sub-circuit simulations are aligned internal to the circuit and externally to the test bench.
Robust verification of analog and mixed signal circuits generally necessitates a significant investment in test benches, performance analysis routines, and macro-models that may be used to accelerate the simulations. The complexity of this collateral grows with the complexity of the analog and mixed signal integrated circuits. As a design team adds design resources it also needs to add verification resources, adding to the cost of the design. The efficient use of those resources becomes paramount due to the inevitable time constraints that are imposed at the end of the design cycle, when companies are trying to get a product to market.
The current technology trajectory within the electronics manufacturing industry is to move more and more toward single chip designs, called Systems on a Chip (SoC). Most systems on a chip generally necessitate some level of mixed signal verification. As mixed signal designs continue to increase in size and complexity, this places additional burdens on verification to insure first pass design success and reducing time-to-market. Although the complexity of analog and mixed signal ASIC design has aggressively followed Moore's law, innovations in design verification generally have not.
Valuable design time and compute resources as well as expensive simulator resources may be saved by the disclosed method for achieving verification coverage based on passive data collection of simulations that have been and are being run. This historical sampling and analysis allows an alignment of test conditions within hierarchies and between hierarchies to insure that duplicate tests are avoided and that untested conditions are identified.
Therefore the disclosure implements improved verification efficiency through utilization of historical data acquired through passive recording and analysis. These and other potential advantageous, features, and benefits of the present disclosure may be understood by one skilled in the arts upon careful consideration of the detailed description of representative examples of the disclosure in connection with the accompanying drawings.